1. Field of the Invention
The present invention relates to a technology of prediction of a polishing condition on which a thin film on a semiconductor device is polished.
2. Description of the Related Art
According to microfabrication and multiple layer wiring of a semiconductor device, flatness is required in each layer. Specifically, in terms of improvement of quality, it is important to polish a surface of a substrate on which copper plating or the like is applied, by a chemical mechanical planarization (CMP) or the like, to obtain uniform flatness in a wiring process in semiconductor device fabrication.
A polishing condition is important to properly polish the copper plating formed on the substrate. The polishing condition should vary according to the thickness of the copper plating. Specifically, the polishing condition is determined based on the combination of a polishing time, a polishing pressure, and a polishing rotational speed when the copper plating is polished by a polishing pad, for example.
A polishing condition for copper plating formed on a substrate is conventionally determined by using a test substrate called a test element group (TEG). For example, the TEG is polished at a certain polishing rotational speed under a certain polishing pressure, and then, the height of the copper plating formed on the substrate and the uneven depth of the copper plating are measured.
Next, calibration is carried out based on the measurement result, and then, a parameter of a simulation model in polishing prediction is extracted. A polishing condition is determined by carrying out a polishing prediction simulation by using the extracted parameter (for example, Japanese Patent Application Laid-open No. 2004-516680).
However, a series of operations are required to be repeated when the polishing pressure and the polishing rotational speed during the polishing are changed in the TEG measurement by the above conventional technique. Therefore, it requires much working time for searching an optimum polishing condition, thereby increasing the design period and labor.
An optimum polishing condition may be searched by changing only the polishing time. However, it is difficult to optimize both of the height of the copper plating formed on the substrate and the groove depth of the copper plating at the same time, thereby making it impossible to establish the optimum polishing condition.
As a result, the substrate cannot be planarized, and therefore, a short is caused in the wiring due to contact of wirings or a focus is inconveniently shifted in forming a wiring pattern, thereby reducing the yield.